Various forms of logic array devices have been in use for years. These devices have architectures based on various combinations of gate arrays, such as programmable-AND/programmable-OR, programmable-AND/fixed-OR, NOR/NOR, etc. While these devices have the flexibility to provide a large number of different custom logic functions, their power consumption can be quite high. This is largely because each logic gate within a gate array continually consumes as much as 20 milliWatts of power. The heat generated by the power consumption combined with the limited heat-sinking capability of the devices and their packages creates a practical gate count limit for such logic devices.
Early forms of logic array device used mask-programmable array elements based on bipolar transistor technologies. Later devices were introduced which used fusible links as array elements, allowing the devices to be programmed after manufacturing. Prior U.S. patents describing these early logic array devices include U.S. Pat. Nos. 3,541,543; 3,566,153; 3,702,985; 3,816,725; 3,818,452; and 3,849,638. More recently, programmable logic devices based on CMOS technology have been introduced. Two of these devices are described by Hartmann et al. in U.S. Pat. Nos. 4,609,986 and 4,617,479. These devices use EPROM or EEPROM transistors as the logic array elements. For a given gate count, these CMOS devices operate at lower power levels, because the circuitry surrounding the logic arrays generally does not consume power. For this reason, the introduction of these CMOS-based logic devices has helped to raise the gate count limit. However, the logic gate arrays themselves are still continually drawing current and therefore consuming power.
Another way to increase the permissible gate count for logic array devices is to simply reduce the current drawn by each array gate. However, this approach decreases the speed performance of the device and makes it unsuitable for applications that require high operating speed.
A circuit operation common to many logic array devices is the transmission gating of logic signals from an input terminal to an output terminal. U.S. Pat. No. 4,713,792 to Hartmann et al. describes one implementation of this operation. Available implementations of transmission gating have so far had limitations of either actively consumed power or less than optimum switching speed.
It is an object of the present invention to provide a logic array device with means for reducing the power consumption without substantially affecting the speed performance or logic function of the device.